1. Field of the Invention
The present invention relates to a bus emulation apparatus for transferring data between peripheral circuits via a hub circuit.
2. Description of the Related Art
A hub or a network having a hub is described in the Japanese Unexamined Patent Publication Nos. 11-284636, No.11-168493, 11-88397, 62-220047 and 7-297853.
For example, Japanese Unexamined Patent Publication No. 11-284636 discloses a hub apparatus and a USB (Universal Serial Bus) communication system. This publication discloses an addition of a function of directly connecting data paths between devices to the hub apparatus.
Japanese Unexamined Patent Publication No. 11-88397 discloses a switching hub. In this publication, a serial/parallel converter is provided among a plurality of high speed network interface portions and a plurality of low speed network switching portions, the data transfer is performed in a serial data within the high speed network interface portion and in a parallel data within the low speed switching portion, and the data transfer rate can be switched.
The Japanese Unexamined Patent Publication No. 7-297853 discloses the polling of a remote station in an extensible round-robin local area network.
In a cabinet of a personal computer and a digital home-use electricity apparatus of the related art, a multi-drop connection mode used a parallel wired bus is generally used.
In such the connection mode of the related art, since the flattening and terminating of an impedance of the wiring path is difficult, it is difficult to raise a data transfer rate per one signal line. Therefore, the number of the wires increases and it suffers from the disadvantages of an increase of a wiring area, an increase of an electro magnetic interference (EMI), a limit of a wiring length, etc.
Furthermore, in a bus wiring and bus architecture of a large-scale integrated circuit (LSI) or a print circuit board of the related art, when transferring a digital signal such as an audio, a video, etc. between peripheral circuits, it is difficult to transfer other signal between other peripheral circuits at a same time.
Therefore, a bus emulation apparatus for satisfying functions of a parallel bus wiring, bus driver, bus receiver, etc. of the related art and overcoming the disadvantages in the existing bus as explained above has been demanded.
Note that serial network standards, such as the IEEE (Institute of Electrical and Electronics Engineers) 1394, Universal Serial Bus (USB) and Eithernet, are basically a Time-Division Multiple Access (TDMA) system, so it is difficult to perform a simultaneous multiple transfers in the same way as in a normal bus.
A wide area network using telephones and an Asynchronous Transfer Mode switching system (ATM) have a hub and spoke type topology, but an objected physical area, a device scale, a timing request, etc. are largely different and is essentially different on a concept to a bus exchange.
A first object of the present invention is to provide a bus emulation apparatus installed on an LSI or a print circuit board and replaceable by a parallel bus.
A second object of the present invention is to provide a bus emulation apparatus capable of transferring data between other peripheral circuits while transferring data between peripheral circuits.
According to the present invention, there is provided a bus emulation apparatus comprising: a hub circuit; a plurality of serial interface circuits; and serial transfer paths for connecting the plurality of serial interface circuits and the hub circuit and being installed on a large scale integrated circuit or a print circuit board, the serial interface circuit comprising: a parallel to serial conversion circuit for converting parallel data from a peripheral circuit connected to the serial interface circuit to a serial data and supplying to the serial transfer path; and a serial to parallel conversion circuit for converting serial data supplied from the hub circuit via the serial transfer path to a parallel data and supplying to the peripheral circuit; and the hub circuit supplying the serial data supplied from the serial interface circuit via the serial transfer path to a serial interface circuit connected to a peripheral circuit as a transfer destination of the parallel data among the plurality of serial interface circuits via the serial transfer path.
Preferably, the hub circuit divides the plurality of serial interface circuit into a plurality of groups for performing data transfers in advance and relays the serial data between the serial interface circuits so that parallel data is transferred in the respective plurality of groups.
Preferably, the serial data supplied from the serial interface circuit to the hub circuit via the serial transfer path comprises an address information indicating a transfer destination; and the hub circuit supplies the serial data to the serial interface circuit connected to a peripheral circuit as the transfer destination based on the address information.
Preferably, the hub circuit comprises a buffer for storing serial data supplied from the serial interface circuit via the serial transfer path; an extraction circuit for extracting address information included in the serial data; a control circuit for determining transfer priority when a plurality of transfer requests exist to a same transfer destination; and a selection circuit for selecting a transfer path of the serial data based on the address information extracted by the extraction circuit and the priority determined by the control circuit.
Alternately, it may be configured that the hub circuit further comprises a detection circuit for detecting transfer end of the serial data form the serial interface circuit and/or an interrupt by the serial interface circuit; and the control circuit determines the priority based on a detection result of the detection circuit.
Alternately, it may be configured that the hub circuit further comprises a clock signal generation circuit for generating a plurality of clock signals having different clock frequencies; and the buffer receives a clock signal from the clock signal generation circuit in accordance with a transfer rate of a peripheral circuit as a transfer source or a transfer destination and inputs/outputs the serial data at a transfer rate in accordance with the supplied clock signal.
Preferably, the hub circuit comprises DMA controllers for controlling transfers of the serial data between the serial interface circuits corresponding to each of the plurality of serial interface circuits.
Preferably, the hub circuit supplies a clock signal to the serial interface circuit via the serial transfer path; and the serial interface circuit supplies the clock signal supplied from the hub circuit to a peripheral circuit operating based on the clock signal and connected to the serial interface circuit.
Alternately, it may be configured that the serial interface circuit comprises a counter for counting the number of data in the buffer in the hub circuit; stops the transmitting the serial data to the hub circuit when a counter value of the counter indicates that the buffer has no vacancy, and transmits the serial data to the hub circuit when the count value of the counter indicates that the buffer has a vacancy.
More preferably, the serial interface circuit, when the parallel data of this time supplied from the peripheral circuit is exactly identical or substantially identical with the preceding parallel data, generates a flag indicating the exactly identity or substantially identity and supplies the generated flag to the hub circuit; and the hub circuit comprises a cache memory for storing preceding serial data corresponding to the preceding parallel data and generates serial data of this time corresponding to the parallel data of this time based on the serial data stored in the cache memory and the flag.
Alternately, it may be configured that the serial interface circuit detects that a difference between the preceding parallel data and the parallel data of this time is xc2x11 and generates the flag indicating the difference; and the hub circuit operates calculation of xc2x11 on the preceding serial data stored in the cache memory based on the flag to generate the serial data of this time.
More preferably, the hub circuit, when the serial data of this time supplied from the serial interface circuit via a serial transfer path is exactly identical or substantially identical with the preceding serial data, generates a flag indicating the exactly identity or substantially identity; and the serial interface circuit connected to a peripheral circuit as a transfer destination comprises a cache memory for storing the preceding parallel data corresponding to the preceding serial data from the hub circuit and generates parallel data of this time based on the parallel data stored in the cache memory and the flag from the hub circuit.
Alternately, it may be configured that the hub circuit detects that a difference between the preceding serial data and the serial data of this time is xc2x11 and generates the flag indicating the difference; and the serial interface circuit connected to a peripheral circuit as the transfer destination operates a calculation of xc2x11 based on the flag on the preceding parallel data stored in the cache memory and generates the parallel data of this time.
More preferably, the serial interface circuit connected to a peripheral circuit as a transfer destination, when the parallel data of this time supplied from the peripheral circuit is exactly identical or substantially identical with the preceding parallel data, generates a flag indicating the exactly identity or substantially identity and supplies the generated flag to the hub circuit; and the serial interface circuit connected to a peripheral circuit of the transfer destination comprises a cache memory for storing the preceding parallel data corresponding to the preceding serial data from the hub circuit and generates the parallel data of this time based on the parallel data stored in the cache memory and the flag from the hub circuit.
Alternately, it may be configured that the serial interface circuit connected to the peripheral circuit of the transfer destination detects that difference between the preceding parallel data and the parallel data of this time is xc2x11 and generates the flag indicating the difference; and the serial interface circuit connected to the peripheral circuit as the transfer destination operates a calculation of xc2x11 on the preceding parallel data stored in the cache memory based on the flag to generate the parallel data of this time.
More preferably, a data length of address information on a most frequently transferred peripheral circuit is shorter than a data length of an address information on a least frequently transferred peripheral circuit.
Preferably, the hub circuit supplies serial data at a plurality of transfer rates to the serial interface circuits and conducts tests of transfer rates; and the serial interface circuit converts the parallel data generated in the serial to parallel conversion circuit to serial data in the parallel to serial conversion circuit and sends back to the hub circuit during the transfer rates tests.
Preferably, the hub circuit conducts connection tests between the plurality of serial interface circuits or self-tests during a spare time of data transfers.
Preferably, the hub circuit has a function of notifying working states of the buffer to a higher controller or a higher system for performing transfer control and/or error recovery.
Preferably, the hub circuit supplies serial data from a specific serial interface circuit among the plurality of serial interface circuits to a serial interface circuit connected to a different peripheral circuit from a peripheral circuit as a transfer destination indicated by address information in the serial data.
Preferably, the parallel to serial conversion circuit converts the parallel data from the peripheral circuit to encoded serial data and supplies to the hub circuit; and the serial to parallel conversion circuit converts the encoded serial data from the hub circuit to decoded parallel data.
More preferably, the parallel to serial conversion circuit comprises a first linear feedback shift register for encoding parallel data from the peripheral circuit; the serial to parallel conversion circuit comprises a second linear feedback shift register for decoding encoded serial data from the hub circuit; and the first and second linear feedback shift registers mutually operate an inverse calculation.
Alternately, it may be configured that an operation frequency of the first linear feedback shift register during an encoding operation is higher than an operation frequency during a transmission operation for shifting and transmitting the encoded serial data.
Alternately, it may be configured that an operation frequency of the second linear feedback shift register during a decoding operation is higher than an operation frequency during a receiving operation for shifting and receiving the encoded serial data from the hub circuit.
Alternately, it may be configured that the serial interface circuit further comprises a register for storing identification information or encoding key information and supplies backup power to the register during a power source failure.
Preferably, a signal line of the serial transfer path is terminated by a terminal resistance, and the terminal resistance comprises a plurality of transistors connected in parallel, the plurality of transistors are selectively set to be an on state and the terminal resistence value is set.
Preferably, the hub circuit and the serial interface circuit further comprises a driver for transmitting serial data to the serial transfer path; and a receiver for receiving serial data from the serial transfer path; and the wire for shielding a signal line of the serial transfer path and a supply line of a drive voltage of the driver and receiver are connected.
More preferably, the receiver comprises a differential type amplification circuit for outputting serial data; one input terminal of the differential amplify circuit is connected to a signal line of the serial transfer path; and other input terminal of the differential type amplification circuit is supplied as an input threshold a voltage obtained by dividing the drive voltage.
Preferably, the signal line of the serial transfer path is grounded via capacitors and terminal resistance element connected in series.
Alternately, it may be configured that the wire for shielding the signal line of the serial transfer path and a ground terminal of the terminal resistance element are connected.
The above bus emulation apparatus according to the present invention comprises a hub circuit, a plurality of serial interface circuits and serial transfer paths for connecting between the plurality of serial interface circuits and the hub circuit, respectively.
The bus emulation apparatus is installed on an LSI or a print circuit board.
The serial interface circuit comprises a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplies to a serial transfer path and a serial to parallel conversion circuit for converting serial data from a hub circuit to parallel data and supplies to the peripheral circuit.
The hub circuit supplies serial data supplied from the serial interface circuit to a serial interface circuit connected to a peripheral circuit as a transfer destination of the parallel data.
As explained above, the bus emulation apparatus of the present invention can have the same functions as those in a bus of the related art.